91 lines
2.3 KiB
C
91 lines
2.3 KiB
C
#include "kernel/lib.h"
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#include "kernel/riscv.h"
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#include "kernel/kalloc.h"
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#include "kernel/vm.h"
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#include "kernel/cpu.h"
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#include "kernel/aplic.h"
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Cpu cpus[MAX_CPU];
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extern uint32_t _bss_start;
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extern uint32_t _bss_end;
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extern uint32_t _ram_end;
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void kstrap()
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{
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uint32_t scause;
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__asm__ volatile("csrr %0, scause" : "=r"(scause));
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switch (scause)
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{
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case 0: panic("kstrap: Instruction address misaligned");
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case 1: panic("kstrap: Instruction access fault");
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case 2: panic("kstrap: Illegal instruction");
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case 3: panic("kstrap: Breakpoint");
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case 4: panic("kstrap: Load address misaligned");
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case 5: panic("kstrap: Load access fault");
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case 6: panic("kstrap: Store/AMO address misaligned");
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case 7: panic("kstrap: Store/AMO access fault");
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case 8: panic("kstrap: Environment call from U-mode");
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case 9: panic("kstrap: Environment call from S-mode");
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case 12: panic("kstrap: Instruction page fault");
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case 13: panic("kstrap: Load page fault");
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case 14: panic("kstrap: Reserved");
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case 15: panic("kstrap: Store/AMO page fault");
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case 18: panic("kstrap: Software check");
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case 19: panic("kstrap: Hardware error");
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default: panic("kstrap: Unknown");
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}
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}
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void uart_init()
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{
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volatile char* UART_BASE = (volatile char*)0x1000'0000;
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// Set LCR[1:0] to 0b11 for 8-bit words
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*(UART_BASE + 3) = 0b0000'0011;
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// Set FCR[0] to 1 to enable FIFO
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*(UART_BASE + 2) = 0b0000'0001;
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// Set IER[0] to 1 to enable interrupts on receive
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*(UART_BASE + 1) = 0b0000'0001;
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}
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void kstart()
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{
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uart_init();
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kalloc_init();
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kvm_init();
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aplic_init();
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panic("kstart: end");
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}
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void kinit()
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{
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// @Todo Initialize CPUs
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Cpu null_cpu = {0};
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cpus[0] = null_cpu;
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// Clear the BSS section
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for (uint32_t* ptr = &_bss_start; ptr < &_bss_end; ++ptr)
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{
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*ptr = 0U;
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}
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w_mideleg(0xFFFF);
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w_medeleg(0xFFFF);
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w_sstatus(SSTATUS_SPIE | SSTATUS_SPP_S);
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w_sie(SIE_SEIE);
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w_sepc(&kstart);
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w_stvec(&kstrap);
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w_pmpcfg0(PMPCFG_RW | PMPCFG_X | PMPCFG_TOR);
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w_pmpaddr0(((uint32_t)&_ram_end) >> PMPADDR_SHIFT);
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__asm__ volatile("sret");
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}
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