Multiplication
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@ -45,6 +45,12 @@ static inline uint32_t sign_extend(uint32_t word, uint32_t size)
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return (word ^ mask) - mask;
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}
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static inline uint64_t sign_extend_64(uint64_t word, uint32_t size)
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{
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const uint64_t mask = 1ULL << (size - 1);
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return (word ^ mask) - mask;
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}
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struct Instruction
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{
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uint8_t opcode;
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@ -166,10 +172,13 @@ static void execute_op(Hart* hart, uint32_t instruction)
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const Instruction inst = decode_r_type(instruction);
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if (inst.rd == 0) return;
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uint32_t bank = inst.funct7 & 0x5F;
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if (bank == 0)
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{
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switch (inst.funct3)
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{
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case 0: // ADD, SUB
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if (instruction & 0x40000000)
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if (inst.funct7 & 0x20)
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{
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hart->regs[inst.rd] = hart->regs[inst.rs1] - hart->regs[inst.rs2];
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}
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@ -194,7 +203,7 @@ static void execute_op(Hart* hart, uint32_t instruction)
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{
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const uint32_t shamt = hart->regs[inst.rs2] & 0x1F;
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uint32_t res = hart->regs[inst.rs1] >> shamt;
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if ((instruction & 0x40000000) && shamt > 0) { res = sign_extend(res, 32 - shamt); }
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if ((inst.funct7 & 0x20) && shamt > 0) { res = sign_extend(res, 32 - shamt); }
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hart->regs[inst.rd] = res;
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break;
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}
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@ -205,7 +214,39 @@ static void execute_op(Hart* hart, uint32_t instruction)
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hart->regs[inst.rd] = hart->regs[inst.rs1] & hart->regs[inst.rs2];
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break;
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default:
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assert(!"Unhandled OP-IMM");
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assert(!"Unhandled OP, bank = 0");
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break;
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}
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}
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else if (bank == 1)
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{
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if ((inst.funct3 & 0x8) == 0)
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{
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uint64_t a = hart->regs[inst.rs1];
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uint64_t b = hart->regs[inst.rs2];
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switch (inst.funct3 & 0x3)
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{
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case 1: // MULH
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b = sign_extend_64(b, 32);
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case 2: // MULHSU
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a = sign_extend_64(a, 32);
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case 0: // MUL
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case 3: // MULHU
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break;
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}
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uint64_t r = a * b;
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hart->regs[inst.rd] = (inst.funct3 == 0) ? r & 0xFFFFFFFF : r >> 32;
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}
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else
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{
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assert(!"Unhandled M OP");
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}
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}
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else
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{
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assert(!"Unhandled OP bank");
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}
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}
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@ -292,7 +333,7 @@ static void store_word(Hart* hart, uint32_t address, uint32_t value)
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store_size(hart, address, value, 4);
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}
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static void execute_op_load(Hart* hart, uint32_t instruction)
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static void execute_load(Hart* hart, uint32_t instruction)
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{
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const Instruction inst = decode_i_type(instruction);
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const uint32_t address = hart->regs[inst.rs1] + inst.imm;
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@ -329,7 +370,7 @@ static void execute_op_load(Hart* hart, uint32_t instruction)
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}
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}
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static void execute_op_store(Hart* hart, uint32_t instruction)
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static void execute_store(Hart* hart, uint32_t instruction)
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{
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const Instruction inst = decode_s_type(instruction);
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const uint32_t address = hart->regs[inst.rs1] + inst.imm;
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@ -545,7 +586,7 @@ void execute(Hart* hart, uint32_t instruction)
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switch (instruction & 0x7f)
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{
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case 0x03:
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execute_op_load(hart, instruction);
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execute_load(hart, instruction);
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hart->pc += 4;
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break;
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case 0x0F:
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@ -567,7 +608,7 @@ void execute(Hart* hart, uint32_t instruction)
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break;
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}
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case 0x23:
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execute_op_store(hart, instruction);
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execute_store(hart, instruction);
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hart->pc += 4;
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break;
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case 0x33:
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@ -2,6 +2,7 @@
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#include <inttypes.h>
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#include <assert.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include "emulator/hart.h"
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@ -229,7 +230,42 @@ static void test_branch()
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assert(hart.pc == 124);
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}
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void test()
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static void test_m()
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{
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struct Hart hart = {0};
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hart.regs[1] = 0xFFFFFFFE;
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hart.regs[2] = 4;
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execute(&hart, 0x022081b3); // mul x3, x1, x2
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assert(hart.regs[3] == 0xFFFFFFF8);
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execute(&hart, 0x0220b1b3); // mulhu x3, x1, x2
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assert(hart.regs[3] == 0x00000003);
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execute(&hart, 0x0220a1b3); // mulhsu x3, x1, x2
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assert(hart.regs[3] == 0xFFFFFFFF);
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execute(&hart, 0x022091b3); // mulh x3, x1, x2
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assert(hart.regs[3] == 0xFFFFFFFF);
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hart.regs[1] = 0xFFFFFFFE;
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hart.regs[2] = 0xFFFFFFFE;
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execute(&hart, 0x022081b3); // mul x3, x1, x2
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assert(hart.regs[3] == 0x00000004);
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execute(&hart, 0x0220b1b3); // mulhu x3, x1, x2
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assert(hart.regs[3] == 0xFFFFFFFC);
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execute(&hart, 0x0220a1b3); // mulhsu x3, x1, x2
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assert(hart.regs[3] == 0xFFFFFFFE);
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execute(&hart, 0x022091b3); // mulh x3, x1, x2
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assert(hart.regs[3] == 0x00000000);
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}
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int main(int argc, char* argv[])
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{
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test_addi();
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test_slti_sltiu();
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@ -240,10 +276,6 @@ void test()
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test_jal();
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test_jalr();
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test_branch();
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}
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int main(int argc, char* argv[])
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{
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test();
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test_m();
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return EXIT_SUCCESS;
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}
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