639 lines
17 KiB
C
639 lines
17 KiB
C
#include "emulator/hart.h"
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#include "emulator/bits.h"
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#include "emulator/instruction.h"
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#include "emulator/csr.h"
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#include <stdio.h>
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#include <inttypes.h>
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#define REG_ZERO 0
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#define REG_RA 1
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#define REG_SP 2
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#define REG_GP 3
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#define REG_TP 4
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#define REG_T0 5
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#define REG_T1 6
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#define REG_T2 7
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#define REG_S0 8
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#define REG_S1 9
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#define REG_A0 10
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#define REG_A1 11
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#define REG_A2 12
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#define REG_A3 13
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#define REG_A4 14
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#define REG_A5 15
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#define REG_A6 16
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#define REG_A7 17
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#define REG_S2 18
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#define REG_S3 19
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#define REG_S4 20
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#define REG_S5 21
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#define REG_S6 22
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#define REG_S7 23
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#define REG_S8 24
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#define REG_S9 25
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#define REG_S10 26
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#define REG_S11 27
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#define REG_T3 28
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#define REG_T4 29
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#define REG_T5 30
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#define REG_T6 31
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static void handle_ecall(Hart* hart)
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{
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}
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static inline uint32_t load_size(Hart* hart, uint32_t address, uint32_t size)
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{
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if ((address & 0x80000000) == 0)
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{
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assert(address + size < hart->mem_size);
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uint32_t value = 0;
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memcpy(&value, hart->mem + address, size);
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return value;
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}
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return 0;
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}
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static uint32_t load_byte(Hart* hart, uint32_t address)
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{
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return load_size(hart, address, 1);
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}
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static uint32_t load_half(Hart* hart, uint32_t address)
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{
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return load_size(hart, address, 2);
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}
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static uint32_t load_word(Hart* hart, uint32_t address)
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{
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return load_size(hart, address, 4);
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}
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static inline void store_size(Hart* hart, uint32_t address, uint32_t value, uint32_t size)
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{
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if ((address & 0x80000000) == 0)
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{
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assert(address + size < hart->mem_size);
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memcpy(hart->mem + address, &value, size);
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}
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else if (address == 0x80000000)
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{
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fwrite(&value, 1, size, stdout);
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}
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}
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static void store_byte(Hart* hart, uint32_t address, uint8_t value)
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{
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store_size(hart, address, value, 1);
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}
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static void store_half(Hart* hart, uint32_t address, uint16_t value)
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{
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store_size(hart, address, value, 2);
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}
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static void store_word(Hart* hart, uint32_t address, uint32_t value)
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{
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store_size(hart, address, value, 4);
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}
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static void execute_op_imm(Hart* hart, uint32_t instruction)
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{
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const Instruction inst = decode_i_type(instruction);
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if (inst.rd == 0) return;
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switch (inst.funct3)
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{
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case 0: // ADDI
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hart->regs[inst.rd] = hart->regs[inst.rs1] + inst.imm;
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break;
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case 1: // SLLI
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hart->regs[inst.rd] = hart->regs[inst.rs1] << (inst.imm & 0x1F);
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break;
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case 2: // SLTI
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hart->regs[inst.rd] = (int32_t)hart->regs[inst.rs1] < (int32_t)inst.imm ? 1 : 0;
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break;
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case 3: // SLTIU
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hart->regs[inst.rd] = hart->regs[inst.rs1] < inst.imm ? 1 : 0;
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break;
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case 4: // XORI
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hart->regs[inst.rd] = hart->regs[inst.rs1] ^ inst.imm;
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break;
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case 5: // SRLI, SRAI
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{
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const uint32_t shamt = inst.imm & 0x1F;
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uint32_t res = hart->regs[inst.rs1] >> shamt;
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if ((inst.imm & 0x400) && shamt > 0) { res = sign_extend(res, 32 - shamt); }
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hart->regs[inst.rd] = res;
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break;
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}
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case 6: // ORI
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hart->regs[inst.rd] = hart->regs[inst.rs1] | inst.imm;
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break;
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case 7: // ANDI
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hart->regs[inst.rd] = hart->regs[inst.rs1] & inst.imm;
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break;
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default:
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assert(!"Unhandled OP-IMM");
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}
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}
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static void execute_op(Hart* hart, uint32_t instruction)
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{
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const Instruction inst = decode_r_type(instruction);
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if (inst.rd == 0) return;
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uint32_t bank = inst.funct7 & 0x5F;
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if (bank == 0)
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{
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switch (inst.funct3)
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{
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case 0: // ADD, SUB
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if (inst.funct7 & 0x20)
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{
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hart->regs[inst.rd] = hart->regs[inst.rs1] - hart->regs[inst.rs2];
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}
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else
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{
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hart->regs[inst.rd] = hart->regs[inst.rs1] + hart->regs[inst.rs2];
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}
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break;
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case 1: // SLL
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hart->regs[inst.rd] = hart->regs[inst.rs1] << (hart->regs[inst.rs2] & 0x1F);
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break;
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case 2: // SLT
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hart->regs[inst.rd] = (int32_t)hart->regs[inst.rs1] < (int32_t)hart->regs[inst.rs2] ? 1 : 0;
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break;
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case 3: // SLTU
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hart->regs[inst.rd] = hart->regs[inst.rs1] < hart->regs[inst.rs2] ? 1 : 0;
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break;
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case 4: // XOR
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hart->regs[inst.rd] = hart->regs[inst.rs1] ^ hart->regs[inst.rs2];
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break;
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case 5: // SRL, SRA
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{
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const uint32_t shamt = hart->regs[inst.rs2] & 0x1F;
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uint32_t res = hart->regs[inst.rs1] >> shamt;
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if ((inst.funct7 & 0x20) && shamt > 0) { res = sign_extend(res, 32 - shamt); }
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hart->regs[inst.rd] = res;
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break;
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}
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case 6: // OR
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hart->regs[inst.rd] = hart->regs[inst.rs1] | hart->regs[inst.rs2];
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break;
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case 7: // AND
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hart->regs[inst.rd] = hart->regs[inst.rs1] & hart->regs[inst.rs2];
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break;
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default:
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assert(!"Unhandled OP, bank = 0");
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break;
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}
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}
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else if (bank == 1)
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{
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if ((inst.funct3 & 0x4) == 0)
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{
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uint64_t a = hart->regs[inst.rs1];
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uint64_t b = hart->regs[inst.rs2];
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switch (inst.funct3 & 0x3)
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{
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case 1: // MULH
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b = sign_extend_64(b, 32);
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case 2: // MULHSU
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a = sign_extend_64(a, 32);
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case 0: // MUL
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case 3: // MULHU
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break;
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}
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uint64_t r = a * b;
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hart->regs[inst.rd] = (inst.funct3 == 0) ? r & 0xFFFFFFFF : r >> 32;
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}
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else
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{
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uint32_t a = hart->regs[inst.rs1];
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uint32_t b = hart->regs[inst.rs2];
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switch (inst.funct3 & 0x3)
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{
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case 0: // DIV
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{
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if (b == 0)
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{
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hart->regs[inst.rd] = 0xFFFFFFFF;
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}
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else if (a == 0x80000000 && b == 0xFFFFFFFF)
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{
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hart->regs[inst.rd] = 0x80000000;
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}
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else
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{
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hart->regs[inst.rd] = (uint32_t)((int32_t)a / (int32_t)b);
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}
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break;
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}
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case 1: // DIVU
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{
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if (b == 0)
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{
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hart->regs[inst.rd] = 0xFFFFFFFF;
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}
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else
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{
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hart->regs[inst.rd] = a / b;
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}
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break;
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}
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case 2: // REM
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{
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if (b == 0)
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{
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hart->regs[inst.rd] = a;
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}
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else if (a == 0x80000000 && b == 0xFFFFFFFF)
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{
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hart->regs[inst.rd] = 0;
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}
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else
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{
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hart->regs[inst.rd] = (uint32_t)((int32_t)a % (int32_t)b);
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}
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break;
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}
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case 3: // REMU
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{
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if (b == 0)
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{
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hart->regs[inst.rd] = a;
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}
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else
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{
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hart->regs[inst.rd] = a % b;
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}
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break;
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}
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}
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}
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}
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else
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{
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assert(!"Unhandled OP bank");
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}
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}
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static void execute_branch(Hart* hart, uint32_t instruction)
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{
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const Instruction inst = decode_b_type(instruction);
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const uint32_t r1 = hart->regs[inst.rs1];
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const uint32_t r2 = hart->regs[inst.rs2];
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bool take_branch = false;
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switch (inst.funct3)
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{
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case 0: take_branch = (r1 == r2); break;
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case 1: take_branch = (r1 != r2); break;
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case 4: take_branch = (r1 < r2); break;
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case 5: take_branch = (r1 >= r2); break;
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case 6: take_branch = ((int32_t)r1 < (int32_t)r2); break;
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case 7: take_branch = ((int32_t)r1 >= (int32_t)r2); break;
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}
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if (take_branch)
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{
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hart->pc += inst.imm;
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}
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else
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{
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hart->pc += 4;
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}
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}
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static void execute_load(Hart* hart, uint32_t instruction)
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{
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const Instruction inst = decode_i_type(instruction);
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const uint32_t address = hart->regs[inst.rs1] + inst.imm;
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uint32_t value = 0;
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switch (inst.funct3 & 0x03)
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{
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case 0:
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value = load_byte(hart, address);
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if ((inst.funct3 & 0x40) == 0)
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{
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value = sign_extend(value, 8);
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}
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break;
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case 1:
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value = load_half(hart, address);
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if ((inst.funct3 & 0x40) == 0)
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{
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value = sign_extend(value, 16);
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}
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break;
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case 2:
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value = load_byte(hart, address);
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break;
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default:
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assert(!"Unhandled load size");
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break;
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}
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if (inst.rd != 0)
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{
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hart->regs[inst.rd] = value;
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}
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}
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static void execute_store(Hart* hart, uint32_t instruction)
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{
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const Instruction inst = decode_s_type(instruction);
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const uint32_t address = hart->regs[inst.rs1] + inst.imm;
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const uint32_t value = hart->regs[inst.rs2];
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switch (inst.funct3 & 0x03)
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{
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case 0: store_byte(hart, address, value & 0xFF); break;
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case 1: store_half(hart, address, value & 0xFFFF); break;
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case 2: store_word(hart, address, value); break;
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default:
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assert(!"Unhandled store size");
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break;
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}
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}
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static void execute_misc_mem(Hart* hart, uint32_t instruction)
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{
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const Instruction inst = decode_i_type(instruction);
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if (inst.funct3 == 0)
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{
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// FENCE
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}
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else
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{
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assert(!"Unhandled MISC-MEM instruction");
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}
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}
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static void execute_system(Hart* hart, uint32_t instruction)
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{
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const Instruction inst = decode_i_type(instruction);
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switch (inst.funct3)
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{
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case 0:
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{
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if (inst.rs1 == 0 && inst.rd == 0)
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{
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if (inst.imm == 0)
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{
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handle_ecall(hart);
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}
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else if (inst.imm == 1)
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{
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// EBREAK
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}
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else
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{
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assert(!"Unhandled SYSTEM/PRIV instruction");
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}
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}
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else
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{
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assert(!"Unhandled SYSTEM/PRIV instruction");
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}
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break;
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}
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case 1: // CSRRW
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{
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uint16_t csr_id = inst.imm & 0xFFF;
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if (inst.rd == 0)
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{
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csr_action(hart, csr_id, hart->regs[inst.rs1], CSR_W);
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}
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else
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{
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hart->regs[inst.rd] = csr_action(hart, csr_id, hart->regs[inst.rs1], CSR_RW);
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}
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break;
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}
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case 2: // CSRRS
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{
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uint16_t csr_id = inst.imm & 0xFFF;
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uint32_t value = 0;
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if (inst.rs1 == 0)
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{
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value = csr_action(hart, csr_id, 0, CSR_R);
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}
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else
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{
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value = csr_action(hart, csr_id, hart->regs[inst.rs1], CSR_RS);
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}
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if (inst.rd != 0)
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{
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hart->regs[inst.rd] = value;
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}
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break;
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}
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case 3: // CSRRC
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{
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uint16_t csr_id = inst.imm & 0xFFF;
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uint32_t value = 0;
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if (inst.rs1 == 0)
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{
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value = csr_action(hart, csr_id, 0, CSR_R);
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}
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else
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{
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value = csr_action(hart, csr_id, hart->regs[inst.rs1], CSR_RC);
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}
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if (inst.rd != 0)
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{
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hart->regs[inst.rd] = value;
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}
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break;
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}
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case 5: // CSRRWI
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{
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uint16_t csr_id = inst.imm & 0xFFF;
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if (inst.rd == 0)
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{
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csr_action(hart, csr_id, inst.rs1, CSR_W);
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}
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else
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{
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hart->regs[inst.rd] = csr_action(hart, csr_id, inst.rs1, CSR_RW);
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}
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break;
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}
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case 6: // CSRRSI
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{
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uint16_t csr_id = inst.imm & 0xFFF;
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uint32_t value = 0;
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if (inst.rs1 == 0)
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{
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value = csr_action(hart, csr_id, 0, CSR_R);
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}
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else
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{
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value = csr_action(hart, csr_id, inst.rs1, CSR_RS);
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}
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if (inst.rd != 0)
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{
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hart->regs[inst.rd] = value;
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}
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break;
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}
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case 7: // CSRRCI
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{
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uint16_t csr_id = inst.imm & 0xFFF;
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uint32_t value = 0;
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if (inst.rs1 == 0)
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{
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value = csr_action(hart, csr_id, 0, CSR_R);
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}
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else
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{
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value = csr_action(hart, csr_id, inst.rs1, CSR_RC);
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}
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if (inst.rd != 0)
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{
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hart->regs[inst.rd] = value;
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}
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break;
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}
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default:
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assert(!"Unhandled SYSTEM instruction");
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break;
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}
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}
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void execute(Hart* hart, uint32_t instruction)
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{
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// @Todo Better time (same on all cores)
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// @Todo Memory-map mtime and mtimecmp
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hart->time = __rdtsc();
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switch (instruction & 0x7f)
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{
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case 0x03:
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execute_load(hart, instruction);
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hart->pc += 4;
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break;
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case 0x0F:
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execute_misc_mem(hart, instruction);
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hart->pc += 4;
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break;
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case 0x13:
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execute_op_imm(hart, instruction);
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hart->pc += 4;
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break;
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case 0x17: // AUIPC
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{
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Instruction inst = decode_u_type(instruction);
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if (inst.rd != 0)
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{
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hart->regs[inst.rd] = inst.imm + hart->pc;
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}
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hart->pc += 4;
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break;
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}
|
|
case 0x23:
|
|
execute_store(hart, instruction);
|
|
hart->pc += 4;
|
|
break;
|
|
case 0x33:
|
|
execute_op(hart, instruction);
|
|
hart->pc += 4;
|
|
break;
|
|
case 0x37: // LUI
|
|
{
|
|
Instruction inst = decode_u_type(instruction);
|
|
if (inst.rd != 0)
|
|
{
|
|
hart->regs[inst.rd] = inst.imm;
|
|
}
|
|
hart->pc += 4;
|
|
break;
|
|
}
|
|
case 0x63:
|
|
execute_branch(hart, instruction);
|
|
break;
|
|
case 0x67: // JALR
|
|
{
|
|
Instruction inst = decode_i_type(instruction);
|
|
assert(inst.funct3 == 0);
|
|
if (inst.rd != 0)
|
|
{
|
|
hart->regs[inst.rd] = hart->pc + 4;
|
|
}
|
|
hart->pc = (hart->regs[inst.rs1] + inst.imm) & 0xFFFFFFFE;
|
|
break;
|
|
}
|
|
case 0x6F: // JAL
|
|
{
|
|
Instruction inst = decode_j_type(instruction);
|
|
if (inst.rd != 0)
|
|
{
|
|
hart->regs[inst.rd] = hart->pc + 4;
|
|
}
|
|
hart->pc += inst.imm;
|
|
break;
|
|
}
|
|
case 0x73:
|
|
{
|
|
execute_system(hart, instruction);
|
|
hart->pc += 4;
|
|
break;
|
|
}
|
|
default:
|
|
assert(!"Unhandled opcode");
|
|
}
|
|
|
|
assert(hart->regs[0] == 0);
|
|
|
|
hart->instret += 1;
|
|
}
|
|
|
|
void execute_from(Hart* hart, uint32_t start_address)
|
|
{
|
|
hart->pc = start_address;
|
|
|
|
while (true)
|
|
{
|
|
uint32_t instruction = load_word(hart, hart->pc);
|
|
execute(hart, instruction);
|
|
}
|
|
}
|
|
|
|
void csr_init(Hart* hart);
|
|
|
|
void hart_init(Hart* hart, uint32_t id, char* mem, uint32_t mem_size)
|
|
{
|
|
memset(hart, 0, sizeof(Hart));
|
|
hart->hartid = id;
|
|
hart->priv = PRIV_M;
|
|
hart->mem = mem;
|
|
hart->mem_size = mem_size;
|
|
|
|
csr_init(hart);
|
|
}
|