OS Hello world

.gitignore

@@ -1 +1 @@
-*.exe
+build

build.bat

@@ -1,2 +1,14 @@
-clang main.c -o riscv.exe -std=c11
+@echo off
+
+SET BUILD_OPTS= -std=c11 -D_CRT_SECURE_NO_WARNINGS -I.
+
+IF NOT EXIST build mkdir build
+
+clang emulator/lib.c -o build/emulator.lib %BUILD_OPTS% -fuse-ld=llvm-lib
+
+clang emulator/main.c build/emulator.lib -o build/emulator.exe %BUILD_OPTS%
+
+clang emulator/hart_test.c build/emulator.lib -o build/hart_test.exe %BUILD_OPTS%
+
+clang --target=riscv32 -march=rv32i -e _main -nostdlib main.asm -o build/main.bin
 

compile_flags.txt

@@ -0,0 +1,2 @@
+-I.
+-D_CRT_SECURE_NO_WARNINGS

emulator/bits.h

@@ -0,0 +1,15 @@
+#pragma once
+
+#include <stdint.h>
+
+static inline uint32_t sign_extend(uint32_t word, uint32_t size)
+{
+    const uint32_t mask = 1U << (size - 1);
+    return (word ^ mask) - mask;
+}
+
+static inline uint64_t sign_extend_64(uint64_t word, uint32_t size)
+{
+    const uint64_t mask = 1ULL << (size - 1);
+    return (word ^ mask) - mask;
+}

emulator/csr.c

@@ -0,0 +1,51 @@
+#include "emulator/csr.h"
+
+#include "emulator/hart.h"
+
+#include <stdbool.h>
+
+static inline uint8_t csr_priv(uint16_t id)
+{
+    return (id & 0x300) >> 8;
+}
+
+static inline bool csr_writable(uint16_t id)
+{
+    return (id & 0xC00) == 0xC00;
+}
+
+uint32_t csr_action(Hart* hart, uint16_t id, uint32_t value, enum CsrAction action)
+{
+    // @Todo exceptions (bad access (rw, level), non existent, etc)
+    if (id > 4096 || hart->csrs[id].action)
+    {
+        // @Todo
+        return 0;
+    }
+
+    if (action > CSR_R && csr_writable(id))
+    {
+        // @Todo
+        return 0;
+    }
+
+    if (csr_priv(id) > hart->priv)
+    {
+        // @Todo
+        return 0;
+    }
+
+    return hart->csrs[id].action(hart, value, action);
+}
+
+void csr_init_unpriv_counter_timer(Hart* hart);
+void csr_init_machine_trap_setup(Hart* hart);
+void csr_init_machine_information(Hart* hart);
+
+void csr_init(Hart* hart)
+{
+    csr_init_unpriv_counter_timer(hart);
+    csr_init_machine_trap_setup(hart);
+    csr_init_machine_information(hart);
+}
+

emulator/csr.h

@@ -0,0 +1,36 @@
+#pragma once
+
+#include <stdint.h>
+
+typedef struct Hart Hart;
+
+#define CSR_CYCLE        0xC00
+#define CSR_CYCLEH       0xC80
+#define CSR_INSTRET      0xC02
+#define CSR_INSTRETH     0xC82
+#define CSR_TIME         0xC01
+#define CSR_TIMEH        0xC81
+
+#define CSR_MVENDORID    0xF11
+#define CSR_MARCHID      0xF12
+#define CSR_MIMPID       0xF13
+#define CSR_MHARTID      0xF14
+
+#define CSR_MISA         0x301
+
+enum CsrAction
+{
+    CSR_R    = 0,
+    CSR_W    = 1,
+    CSR_RW   = 3,
+    CSR_RC   = 5,
+    CSR_RS   = 7,
+};
+
+struct Csr
+{
+    uint32_t (*action)(Hart* hart, uint32_t value_mask, enum CsrAction action);
+};
+typedef struct Csr Csr;
+
+uint32_t csr_action(Hart* hart, uint16_t id, uint32_t value, enum CsrAction action);

emulator/csr_machine_information.c

@@ -0,0 +1,21 @@
+#include "emulator/csr.h"
+
+#include "emulator/hart.h"
+
+static uint32_t csr_minfo_zero(Hart* hart, uint32_t v, enum CsrAction a)
+{
+    return 0;
+}
+
+static uint32_t csr_mhartid(Hart* hart, uint32_t v, enum CsrAction a)
+{
+    return hart->hartid;
+}
+
+void csr_init_machine_information(Hart* hart)
+{
+    hart->csrs[CSR_MVENDORID].action = csr_minfo_zero;
+    hart->csrs[CSR_MARCHID].action = csr_minfo_zero;
+    hart->csrs[CSR_MIMPID].action = csr_minfo_zero;
+    hart->csrs[CSR_MHARTID].action = csr_mhartid;
+}

emulator/csr_machine_trap_setup.c

@@ -0,0 +1,19 @@
+#include "emulator/csr.h"
+
+#include "emulator/hart.h"
+
+static uint32_t csr_misa(Hart* hart, uint32_t v, enum CsrAction a)
+{
+    uint32_t misa = 0;
+    misa |= 1 << 30; // 32-bit
+    misa |= 1 << 8;  // Base ISA
+    misa |= 1 << 12; // M extension
+    misa |= 1 << 18; // Supervisor mode
+    misa |= 1 << 20; // User mode
+    return misa;
+}
+
+void csr_init_machine_trap_setup(Hart* hart)
+{
+    hart->csrs[CSR_MISA].action = csr_misa;
+}

emulator/csr_unpriv_counter_timer.c

@@ -0,0 +1,33 @@
+#include "emulator/csr.h"
+
+#include "emulator/hart.h"
+
+static uint32_t csr_cycle(Hart* hart, uint32_t v, enum CsrAction a)
+{
+    return hart->instret & 0xFFFFFFFF;
+}
+
+static uint32_t csr_cycleh(Hart* hart, uint32_t v, enum CsrAction a)
+{
+    return hart->instret >> 32;
+}
+
+static uint32_t csr_time(Hart* hart, uint32_t v, enum CsrAction a)
+{
+    return hart->time & 0xFFFFFFFF;
+}
+
+static uint32_t csr_timeh(Hart* hart, uint32_t v, enum CsrAction a)
+{
+    return hart->time >> 32;
+}
+
+void csr_init_unpriv_counter_timer(Hart* hart)
+{
+    hart->csrs[CSR_CYCLE].action = csr_cycle;
+    hart->csrs[CSR_CYCLEH].action = csr_cycleh;
+    hart->csrs[CSR_INSTRET].action = csr_cycle;
+    hart->csrs[CSR_INSTRETH].action = csr_cycleh;
+    hart->csrs[CSR_TIME].action = csr_time;
+    hart->csrs[CSR_TIMEH].action = csr_timeh;
+}

emulator/elf.c

@@ -0,0 +1,133 @@
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+#include <assert.h>
+
+#define ET_NONE 0x00
+#define ET_REL  0x01
+#define ET_EXEC 0x02
+#define ET_DYN  0x03
+#define ET_CORE 0x04
+
+struct Elf32Header
+{
+    uint8_t  ident[16];
+    uint16_t type;
+    uint16_t machine;
+    uint32_t version;
+    uint32_t entry;
+    uint32_t phoff;
+    uint32_t shoff;
+    uint32_t flags;
+    uint16_t ehsize;
+    uint16_t phentsize;
+    uint16_t phnum;
+    uint16_t shentsize;
+    uint16_t shnum;
+    uint16_t shstrndx;
+};
+
+#define PT_NULL    0x00000000
+#define PT_LOAD    0x00000001
+#define PT_DYNAMIC 0x00000002
+#define PT_INTERP  0x00000003
+#define PT_NOTE    0x00000004
+#define PT_SHLIB   0x00000005
+#define PT_PHDR    0x00000006
+#define PT_TLS     0x00000007
+
+#define PF_X 0x1
+#define PF_W 0x2
+#define PF_R 0x4
+
+struct Elf32ProgramHeader
+{
+    uint32_t type;
+    uint32_t offset;
+    uint32_t vaddr;
+    uint32_t paddr;
+    uint32_t filesz;
+    uint32_t memsz;
+    uint32_t flags;
+    uint32_t align;
+};
+
+bool load_elf(const char* file, char* mem, uint32_t mem_size, uint32_t* start_address)
+{
+    FILE* fp = fopen(file, "rb");
+    if (fp == NULL)
+    {
+        printf("Couldn't open input file\n");
+        return false;
+    }
+
+    struct Elf32Header header;
+    size_t read = fread(&header, sizeof(struct Elf32Header), 1, fp);
+    if (read != 1)
+    {
+        printf("ELF header too small\n");
+        return false;
+    }
+
+    static uint8_t kValidIdent[7] = {
+        0x7f, 0x45, 0x4c, 0x46,
+        1, 1, 1
+    };
+    if (memcmp(kValidIdent, header.ident, 7) != 0)
+    {
+        printf("Invalid ELF header\n");
+        return false;
+    }
+
+    if (header.type != ET_EXEC)
+    {
+        printf("Can only link EXEC ELF files\n");
+        return false;
+    }
+
+    memset(mem, 0, mem_size);
+    
+    assert(header.phnum == 0 || header.phentsize == sizeof(struct Elf32ProgramHeader));
+    for (uint32_t i = 0; i < header.phnum; ++i)
+    {
+        struct Elf32ProgramHeader pheader;
+
+        fseek(fp, header.phoff + i * header.phentsize, SEEK_SET);
+        read = fread(&pheader, sizeof(struct Elf32ProgramHeader), 1, fp);
+        if (read != 1)
+        {
+            printf("Error reading program header at index %u\n", i);
+            return false;
+        }
+
+        if (pheader.type == PT_LOAD)
+        {
+            if (pheader.paddr + pheader.memsz > mem_size)
+            {
+                printf("Memory not large enough for ELF file\n");
+                return false;
+            }
+
+            fseek(fp, pheader.offset, SEEK_SET);
+            read = fread(mem + pheader.paddr, pheader.filesz, 1, fp);
+            if (read != 1)
+            {
+                printf("Error when copying ELF segment\n");
+                return false;
+            }
+        }
+    }
+
+    if (header.entry > mem_size)
+    {
+        printf("Entry address out of bounds\n");
+        return false;
+    }
+
+    *start_address = header.entry;
+    fclose(fp);
+
+    return true;
+}

emulator/elf.h

@@ -0,0 +1,6 @@
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+
+bool load_elf(const char* file, char* mem, uint32_t mem_size, uint32_t* start_address);

emulator/hart.c

@@ -0,0 +1,638 @@
+#include "emulator/hart.h"
+
+#include "emulator/bits.h"
+#include "emulator/instruction.h"
+#include "emulator/csr.h"
+
+#include <stdio.h>
+#include <inttypes.h>
+#include <assert.h>
+#include <stdbool.h>
+#include <string.h>
+
+#define REG_ZERO 0
+#define REG_RA   1
+#define REG_SP   2
+#define REG_GP   3
+#define REG_TP   4
+#define REG_T0   5
+#define REG_T1   6
+#define REG_T2   7
+#define REG_S0   8
+#define REG_S1   9
+#define REG_A0   10
+#define REG_A1   11
+#define REG_A2   12
+#define REG_A3   13
+#define REG_A4   14
+#define REG_A5   15
+#define REG_A6   16
+#define REG_A7   17
+#define REG_S2   18
+#define REG_S3   19
+#define REG_S4   20
+#define REG_S5   21
+#define REG_S6   22
+#define REG_S7   23
+#define REG_S8   24
+#define REG_S9   25
+#define REG_S10  26
+#define REG_S11  27
+#define REG_T3   28
+#define REG_T4   29
+#define REG_T5   30
+#define REG_T6   31
+
+static void handle_ecall(Hart* hart)
+{
+}
+
+static inline uint32_t load_size(Hart* hart, uint32_t address, uint32_t size)
+{
+    if ((address & 0x80000000) == 0)
+    {
+        assert(address + size < hart->mem_size);
+        uint32_t value = 0;
+        memcpy(&value, hart->mem + address, size);
+        return value;
+    }
+    
+    return 0;
+}
+
+static uint32_t load_byte(Hart* hart, uint32_t address)
+{
+    return load_size(hart, address, 1);
+}
+
+static uint32_t load_half(Hart* hart, uint32_t address)
+{
+    return load_size(hart, address, 2);
+}
+
+static uint32_t load_word(Hart* hart, uint32_t address)
+{
+    return load_size(hart, address, 4);
+}
+
+static inline void store_size(Hart* hart, uint32_t address, uint32_t value, uint32_t size)
+{
+    if ((address & 0x80000000) == 0)
+    {
+        assert(address + size < hart->mem_size);
+        memcpy(hart->mem + address, &value, size);
+    }
+    else if (address == 0x80000000)
+    {
+        fwrite(&value, 1, size, stdout);
+    }
+}
+
+static void store_byte(Hart* hart, uint32_t address, uint8_t value)
+{
+    store_size(hart, address, value, 1);
+}
+
+static void store_half(Hart* hart, uint32_t address, uint16_t value)
+{
+    store_size(hart, address, value, 2);
+}
+
+static void store_word(Hart* hart, uint32_t address, uint32_t value)
+{
+    store_size(hart, address, value, 4);
+}
+
+static void execute_op_imm(Hart* hart, uint32_t instruction)
+{
+    const Instruction inst = decode_i_type(instruction);
+    if (inst.rd == 0) return;
+    
+    switch (inst.funct3)
+    {
+        case 0: // ADDI
+            hart->regs[inst.rd] = hart->regs[inst.rs1] + inst.imm;
+            break;
+        case 1: // SLLI
+            hart->regs[inst.rd] = hart->regs[inst.rs1] << (inst.imm & 0x1F);
+            break;
+        case 2: // SLTI
+            hart->regs[inst.rd] = (int32_t)hart->regs[inst.rs1] < (int32_t)inst.imm ? 1 : 0;
+            break;
+        case 3: // SLTIU
+            hart->regs[inst.rd] = hart->regs[inst.rs1] < inst.imm ? 1 : 0;
+            break;
+        case 4: // XORI
+            hart->regs[inst.rd] = hart->regs[inst.rs1] ^ inst.imm;
+            break;
+        case 5: // SRLI, SRAI
+        {
+            const uint32_t shamt = inst.imm & 0x1F;
+            uint32_t res = hart->regs[inst.rs1] >> shamt;
+            if ((inst.imm & 0x400) && shamt > 0) { res = sign_extend(res, 32 - shamt); }
+            hart->regs[inst.rd] = res;
+            break;
+        }
+        case 6: // ORI
+            hart->regs[inst.rd] = hart->regs[inst.rs1] | inst.imm;
+            break;
+        case 7: // ANDI
+            hart->regs[inst.rd] = hart->regs[inst.rs1] & inst.imm;
+            break;
+        default:
+            assert(!"Unhandled OP-IMM");
+    }
+}
+
+static void execute_op(Hart* hart, uint32_t instruction)
+{
+    const Instruction inst = decode_r_type(instruction);
+    if (inst.rd == 0) return;
+
+    uint32_t bank = inst.funct7 & 0x5F;
+    if (bank == 0)
+    {
+        switch (inst.funct3)
+        {
+            case 0: // ADD, SUB
+                if (inst.funct7 & 0x20)
+                {
+                    hart->regs[inst.rd] = hart->regs[inst.rs1] - hart->regs[inst.rs2];
+                }
+                else
+                {
+                    hart->regs[inst.rd] = hart->regs[inst.rs1] + hart->regs[inst.rs2];
+                }
+                break;
+            case 1: // SLL
+                hart->regs[inst.rd] = hart->regs[inst.rs1] << (hart->regs[inst.rs2] & 0x1F);
+                break;
+            case 2: // SLT
+                hart->regs[inst.rd] = (int32_t)hart->regs[inst.rs1] < (int32_t)hart->regs[inst.rs2] ? 1 : 0;
+                break;
+            case 3: // SLTU
+                hart->regs[inst.rd] = hart->regs[inst.rs1] < hart->regs[inst.rs2] ? 1 : 0;
+                break;
+            case 4: // XOR
+                hart->regs[inst.rd] = hart->regs[inst.rs1] ^ hart->regs[inst.rs2];
+                break;
+            case 5: // SRL, SRA
+            {
+                const uint32_t shamt = hart->regs[inst.rs2] & 0x1F;
+                uint32_t res = hart->regs[inst.rs1] >> shamt;
+                if ((inst.funct7 & 0x20) && shamt > 0) { res = sign_extend(res, 32 - shamt); }
+                hart->regs[inst.rd] = res;
+                break;
+            }
+            case 6: // OR
+                hart->regs[inst.rd] = hart->regs[inst.rs1] | hart->regs[inst.rs2];
+                break;
+            case 7: // AND
+                hart->regs[inst.rd] = hart->regs[inst.rs1] & hart->regs[inst.rs2];
+                break;
+            default:
+                assert(!"Unhandled OP, bank = 0");
+                break;
+        }
+    }
+    else if (bank == 1)
+    {
+        if ((inst.funct3 & 0x4) == 0)
+        {
+            uint64_t a = hart->regs[inst.rs1];
+            uint64_t b = hart->regs[inst.rs2];
+
+            switch (inst.funct3 & 0x3)
+            {
+                case 1: // MULH
+                    b = sign_extend_64(b, 32);
+                case 2: // MULHSU
+                    a = sign_extend_64(a, 32);
+                case 0: // MUL
+                case 3: // MULHU
+                    break;
+            }
+
+            uint64_t r = a * b;
+            hart->regs[inst.rd] = (inst.funct3 == 0) ? r & 0xFFFFFFFF : r >> 32;
+        }
+        else
+        {
+            uint32_t a = hart->regs[inst.rs1];
+            uint32_t b = hart->regs[inst.rs2];
+
+            switch (inst.funct3 & 0x3)
+            {
+                case 0: // DIV
+                {
+                    if (b == 0)
+                    {
+                        hart->regs[inst.rd] = 0xFFFFFFFF;
+                    }
+                    else if (a == 0x80000000 && b == 0xFFFFFFFF)
+                    {
+                        hart->regs[inst.rd] = 0x80000000;
+                    }
+                    else
+                    {
+                        hart->regs[inst.rd] = (uint32_t)((int32_t)a / (int32_t)b);
+                    }
+                    break;
+                }
+                case 1: // DIVU
+                {
+                    if (b == 0)
+                    {
+                        hart->regs[inst.rd] = 0xFFFFFFFF;
+                    }
+                    else
+                    {
+                        hart->regs[inst.rd] = a / b;
+                    }
+                    break;
+                }
+                case 2: // REM
+                {
+                    if (b == 0)
+                    {
+                        hart->regs[inst.rd] = a;
+                    }
+                    else if (a == 0x80000000 && b == 0xFFFFFFFF)
+                    {
+                        hart->regs[inst.rd] = 0;
+                    }
+                    else
+                    {
+                        hart->regs[inst.rd] = (uint32_t)((int32_t)a % (int32_t)b);
+                    }
+                    break;
+                }
+                case 3: // REMU
+                {
+                    if (b == 0)
+                    {
+                        hart->regs[inst.rd] = a;
+                    }
+                    else
+                    {
+                        hart->regs[inst.rd] = a % b;
+                    }
+                    break;
+                }
+            }
+        }
+    }
+    else
+    {
+        assert(!"Unhandled OP bank");
+    }
+}
+
+static void execute_branch(Hart* hart, uint32_t instruction)
+{
+    const Instruction inst = decode_b_type(instruction);
+    const uint32_t r1 = hart->regs[inst.rs1];
+    const uint32_t r2 = hart->regs[inst.rs2];
+    bool take_branch = false;
+
+    switch (inst.funct3)
+    {
+        case 0: take_branch = (r1 == r2); break;
+        case 1: take_branch = (r1 != r2); break;
+        case 4: take_branch = (r1 < r2); break;
+        case 5: take_branch = (r1 >= r2); break;
+        case 6: take_branch = ((int32_t)r1 < (int32_t)r2); break;
+        case 7: take_branch = ((int32_t)r1 >= (int32_t)r2); break;
+    }
+
+    if (take_branch)
+    {
+        hart->pc += inst.imm;
+    }
+    else
+    {
+        hart->pc += 4;
+    }
+}
+
+static void execute_load(Hart* hart, uint32_t instruction)
+{
+    const Instruction inst = decode_i_type(instruction);
+    const uint32_t address = hart->regs[inst.rs1] + inst.imm;
+    
+    uint32_t value = 0;
+    
+    switch (inst.funct3 & 0x03)
+    {
+        case 0:
+            value = load_byte(hart, address);
+            if ((inst.funct3 & 0x40) == 0)
+            {
+                value = sign_extend(value, 8);
+            }
+            break;
+        case 1:
+            value = load_half(hart, address);
+            if ((inst.funct3 & 0x40) == 0)
+            {
+                value = sign_extend(value, 16);
+            }
+            break;
+        case 2:
+            value = load_byte(hart, address);
+            break;
+        default:
+            assert(!"Unhandled load size");
+            break;
+    }
+
+    if (inst.rd != 0)
+    {
+        hart->regs[inst.rd] = value;
+    }
+}
+
+static void execute_store(Hart* hart, uint32_t instruction)
+{
+    const Instruction inst = decode_s_type(instruction);
+    const uint32_t address = hart->regs[inst.rs1] + inst.imm;
+    const uint32_t value = hart->regs[inst.rs2];
+
+    switch (inst.funct3 & 0x03)
+    {
+        case 0: store_byte(hart, address, value & 0xFF); break;
+        case 1: store_half(hart, address, value & 0xFFFF); break;
+        case 2: store_word(hart, address, value); break;
+        default:
+            assert(!"Unhandled store size");
+            break;
+    }
+}
+
+static void execute_misc_mem(Hart* hart, uint32_t instruction)
+{
+    const Instruction inst = decode_i_type(instruction);
+    
+    if (inst.funct3 == 0)
+    {
+        // FENCE
+    }
+    else
+    {
+        assert(!"Unhandled MISC-MEM instruction");
+    }
+}
+
+static void execute_system(Hart* hart, uint32_t instruction)
+{
+    const Instruction inst = decode_i_type(instruction);
+
+    switch (inst.funct3)
+    {
+        case 0:
+        {
+            if (inst.rs1 == 0 && inst.rd == 0)
+            {
+                if (inst.imm == 0)
+                {
+                    handle_ecall(hart);
+                }
+                else if (inst.imm == 1)
+                {
+                    // EBREAK
+                }
+                else
+                {
+                    assert(!"Unhandled SYSTEM/PRIV instruction");
+                }
+            }
+            else
+            {
+                assert(!"Unhandled SYSTEM/PRIV instruction");
+            }
+            break;
+        }
+        case 1: // CSRRW
+        {
+            uint16_t csr_id = inst.imm & 0xFFF;
+            
+            if (inst.rd == 0)
+            {
+                csr_action(hart, csr_id, hart->regs[inst.rs1], CSR_W);
+            }
+            else
+            {
+                hart->regs[inst.rd] = csr_action(hart, csr_id, hart->regs[inst.rs1], CSR_RW);
+            }
+            break;
+        }
+        case 2: // CSRRS
+        {
+            uint16_t csr_id = inst.imm & 0xFFF;
+            uint32_t value = 0;
+            
+            if (inst.rs1 == 0)
+            {
+                value = csr_action(hart, csr_id, 0, CSR_R);
+            }
+            else
+            {
+                value = csr_action(hart, csr_id, hart->regs[inst.rs1], CSR_RS);
+            }
+            
+            if (inst.rd != 0)
+            {
+                hart->regs[inst.rd] = value;
+            }
+            break;
+        }
+        case 3: // CSRRC
+        {
+            uint16_t csr_id = inst.imm & 0xFFF;
+            uint32_t value = 0;
+            
+            if (inst.rs1 == 0)
+            {
+                value = csr_action(hart, csr_id, 0, CSR_R);
+            }
+            else
+            {
+                value = csr_action(hart, csr_id, hart->regs[inst.rs1], CSR_RC);
+            }
+            
+            if (inst.rd != 0)
+            {
+                hart->regs[inst.rd] = value;
+            }
+            break;
+        }
+        case 5: // CSRRWI
+        {
+            uint16_t csr_id = inst.imm & 0xFFF;
+            
+            if (inst.rd == 0)
+            {
+                csr_action(hart, csr_id, inst.rs1, CSR_W);
+            }
+            else
+            {
+                hart->regs[inst.rd] = csr_action(hart, csr_id, inst.rs1, CSR_RW);
+            }
+            break;
+        }
+        case 6: // CSRRSI
+        {
+            uint16_t csr_id = inst.imm & 0xFFF;
+            uint32_t value = 0;
+            
+            if (inst.rs1 == 0)
+            {
+                value = csr_action(hart, csr_id, 0, CSR_R);
+            }
+            else
+            {
+                value = csr_action(hart, csr_id, inst.rs1, CSR_RS);
+            }
+            
+            if (inst.rd != 0)
+            {
+                hart->regs[inst.rd] = value;
+            }
+            break;
+        }
+        case 7: // CSRRCI
+        {
+            uint16_t csr_id = inst.imm & 0xFFF;
+            uint32_t value = 0;
+            
+            if (inst.rs1 == 0)
+            {
+                value = csr_action(hart, csr_id, 0, CSR_R);
+            }
+            else
+            {
+                value = csr_action(hart, csr_id, inst.rs1, CSR_RC);
+            }
+            
+            if (inst.rd != 0)
+            {
+                hart->regs[inst.rd] = value;
+            }
+            break;
+        }
+        default:
+            assert(!"Unhandled SYSTEM instruction");
+            break;
+    }
+}
+
+void execute(Hart* hart, uint32_t instruction)
+{
+    // @Todo Better time (same on all cores)
+    // @Todo Memory-map mtime and mtimecmp
+    hart->time = __rdtsc();
+    
+    switch (instruction & 0x7f)
+    {
+        case 0x03:
+            execute_load(hart, instruction);
+            hart->pc += 4;
+            break;
+        case 0x0F:
+            execute_misc_mem(hart, instruction);
+            hart->pc += 4;
+            break;
+        case 0x13:
+            execute_op_imm(hart, instruction);
+            hart->pc += 4;
+            break;
+        case 0x17: // AUIPC
+        {
+            Instruction inst = decode_u_type(instruction);
+            if (inst.rd != 0)
+            {
+                hart->regs[inst.rd] = inst.imm + hart->pc;
+            }
+            hart->pc += 4;
+            break;
+        }
+        case 0x23:
+            execute_store(hart, instruction);
+            hart->pc += 4;
+            break;
+        case 0x33:
+            execute_op(hart, instruction);
+            hart->pc += 4;
+            break;
+        case 0x37: // LUI
+        {
+            Instruction inst = decode_u_type(instruction);
+            if (inst.rd != 0)
+            {
+                hart->regs[inst.rd] = inst.imm;
+            }
+            hart->pc += 4;
+            break;
+        }
+        case 0x63:
+            execute_branch(hart, instruction);
+            break;
+        case 0x67: // JALR
+        {
+            Instruction inst = decode_i_type(instruction);
+            assert(inst.funct3 == 0);
+            if (inst.rd != 0)
+            {
+                hart->regs[inst.rd] = hart->pc + 4;
+            }
+            hart->pc = (hart->regs[inst.rs1] + inst.imm) & 0xFFFFFFFE;
+            break;
+        }
+        case 0x6F: // JAL
+        {
+            Instruction inst = decode_j_type(instruction);
+            if (inst.rd != 0)
+            {
+                hart->regs[inst.rd] = hart->pc + 4;
+            }
+            hart->pc += inst.imm;
+            break;
+        }
+        case 0x73:
+        {
+            execute_system(hart, instruction);
+            hart->pc += 4;
+            break;
+        }
+        default:
+            assert(!"Unhandled opcode");
+    }
+
+    assert(hart->regs[0] == 0);
+
+    hart->instret += 1;
+}
+
+void execute_from(Hart* hart, uint32_t start_address)
+{
+    hart->pc = start_address;
+
+    while (true)
+    {
+        uint32_t instruction = load_word(hart, hart->pc);
+        execute(hart, instruction);
+    }
+}
+
+void csr_init(Hart* hart);
+
+void hart_init(Hart* hart, uint32_t id, char* mem, uint32_t mem_size)
+{
+    memset(hart, 0, sizeof(Hart));
+    hart->hartid = id;
+    hart->priv = PRIV_M;
+    hart->mem = mem;
+    hart->mem_size = mem_size;
+    
+    csr_init(hart);
+}

emulator/hart.h

@@ -0,0 +1,38 @@
+#pragma once
+
+#include "emulator/csr.h"
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#define PRIV_U 0
+#define PRIV_S 1
+#define PRIV_M 3
+
+struct Hart
+{
+    uint32_t hartid;
+    
+    uint32_t regs[32];
+
+    uint32_t pc;
+    uint8_t  priv;
+    
+    // @Todo Proper memory system
+    char*    mem;
+    uint32_t mem_size;
+
+    // @Todo Deduplicate per machine
+    Csr      csrs[4096];
+
+    uint64_t instret;
+
+    // @Todo Deduplicate per machine
+    uint64_t time;
+};
+typedef struct Hart Hart;
+
+void hart_init(Hart* hart, uint32_t id, char* mem, uint32_t mem_size);
+
+void execute(Hart* hart, uint32_t instruction);
+void execute_from(Hart* hart, uint32_t start_address);

emulator/hart_test.c

@@ -0,0 +1,311 @@
+#include <stdlib.h>
+#include <inttypes.h>
+#include <assert.h>
+#include <stdbool.h>
+#include <stdio.h>
+
+#include "emulator/hart.h"
+
+static void test_addi()
+{
+    struct Hart hart = {0};
+    
+    execute(&hart, 0x00500093); // addi x1, x0, 5
+    assert(hart.regs[1] == 5);
+
+    execute(&hart, 0xffe00093); // addi, x1, x0, -2
+    assert(hart.regs[1] == 0xfffffffe);
+}
+
+static void test_slti_sltiu()
+{
+    struct Hart hart = {0};
+    
+    hart.regs[1] = 5;
+
+    execute(&hart, 0x00f0b113); // sltiu x2, x1, 15
+    assert(hart.regs[2] == 1);
+
+    execute(&hart, 0x0050b113); // sltiu x2, x1, 15
+    assert(hart.regs[2] == 0);
+
+    execute(&hart, 0x0010b113); // sltiu x2, x1, 15
+    assert(hart.regs[2] == 0);
+
+    execute(&hart, 0x00f0a113); // slti x2, x1, 15
+    assert(hart.regs[2] == 1);
+
+    execute(&hart, 0x0050a113); // slti x2, x1, 15
+    assert(hart.regs[2] == 0);
+
+    execute(&hart, 0x0010a113); // slti x2, x1, 15
+    assert(hart.regs[2] == 0);
+
+    execute(&hart, 0xffb0a113); // slti x2, x1, -5
+    assert(hart.regs[2] == 0);
+
+    hart.regs[1] = (uint32_t)-20;
+
+    execute(&hart, 0xffb0a113); // slti x2, x1, -5
+    assert(hart.regs[2] == 1);
+}
+
+static void test_andi_ori_xori()
+{
+    struct Hart hart = {0};
+    
+    hart.regs[1] = 6;
+
+    execute(&hart, 0x00c0c113); // xori x2, x1, 12
+    assert(hart.regs[2] == 10);
+    
+    execute(&hart, 0x00c0e113); // ori x2, x1, 12
+    assert(hart.regs[2] == 14);
+    
+    execute(&hart, 0x00c0f113); // andi x2, x1, 12
+    assert(hart.regs[2] == 4);
+}
+
+static void test_slli_srli_srai()
+{
+    struct Hart hart = {0};
+    
+    hart.regs[1] = 6;
+
+    execute(&hart, 0x00209113); // slli x2, x1, 2
+    assert(hart.regs[2] == 24);
+
+    execute(&hart, 0x0020d113); // srli x2, x1, 2
+    assert(hart.regs[2] == 1);
+
+    execute(&hart, 0x4020d113); // srai x2, x1, 2
+    assert(hart.regs[2] == 1);
+
+    hart.regs[1] = (uint32_t)-6;
+
+    execute(&hart, 0x0020d113); // srli x2, x1, 2
+    assert(hart.regs[2] == 0x3FFFFFFE);
+
+    execute(&hart, 0x4020d113); // srai x2, x1, 2
+    assert(hart.regs[2] == 0xFFFFFFFE);
+}
+
+static void test_lui_auipc()
+{
+    struct Hart hart = {0};
+    
+    hart.pc = 0;
+    execute(&hart, 0x0007b0b7); // lui x1, 503808
+    assert(hart.regs[1] == 503808);
+    
+    hart.pc = 0;
+    execute(&hart, 0x0007b097); // auipc x1, 503808
+    assert(hart.regs[1] == 503808);
+    
+    hart.pc = 12;
+    execute(&hart, 0x0007b097); // auipc x1, 503808
+    assert(hart.regs[1] == 503820);
+}
+
+static void test_op()
+{
+    struct Hart hart = {0};
+
+    hart.regs[1] = 3;
+    hart.regs[2] = 4;
+    hart.regs[4] = (uint32_t)-1;
+
+    execute(&hart, 0x002081b3); // add, x3, x1, x2
+    assert(hart.regs[3] == 7);
+
+    execute(&hart, 0x402081b3); // sub x3, x1, x2
+    assert(hart.regs[3] == 0xFFFFFFFF);
+
+    execute(&hart, 0x0020a1b3); // slt x3, x1, x2
+    assert(hart.regs[3] == 1);
+
+    execute(&hart, 0x001121b3); // slt x3, x2, 1
+    assert(hart.regs[3] == 0);
+
+    execute(&hart, 0x001131b3); // sltu x3, x2, x1
+    assert(hart.regs[3] == 0);
+
+    execute(&hart, 0x0020b1b3); // sltu x3, x1, x2
+    assert(hart.regs[3] == 1);
+
+    execute(&hart, 0x0040a1b3); // slt x3, x1, x4
+    assert(hart.regs[3] == 0);
+    
+    hart.regs[1] = 6;
+    hart.regs[2] = 12;
+
+    execute(&hart, 0x0020e1b3); // or x3, x1, x2
+    assert(hart.regs[3] == 14);
+
+    execute(&hart, 0x0020c1b3); // xor x3, x1, x2
+    assert(hart.regs[3] == 10);
+
+    execute(&hart, 0x0020f1b3); // and x3, x1, x2
+    assert(hart.regs[3] == 4);
+    
+    hart.regs[1] = 6;
+    hart.regs[2] = 2;
+
+    execute(&hart, 0x002091b3); // sll x3, x1, x2
+    assert(hart.regs[3] == 24);
+
+    execute(&hart, 0x0020d1b3); // srl x3, x1, x2
+    assert(hart.regs[3] == 1);
+
+    execute(&hart, 0x4020d1b3); // sra x3, x1, x2
+    assert(hart.regs[3] == 1);
+    
+    hart.regs[1] = (uint32_t)-6;
+    hart.regs[2] = 2;
+
+    execute(&hart, 0x4020d1b3); // sra x3, x1, x2
+    assert(hart.regs[3] == 0xFFFFFFFE);
+}
+
+static void test_jal()
+{
+    struct Hart hart = {0};
+
+    hart.pc = 12;
+
+    execute(&hart, 0x12c000ef); // jal x1, 300
+    assert(hart.regs[1] == 16);
+    assert(hart.pc == 312);
+
+    execute(&hart, 0xed5ff0ef); // jal x1, -300
+    assert(hart.regs[1] == 316);
+    assert(hart.pc == 12);
+}
+
+static void test_jalr()
+{
+    struct Hart hart = {0};
+
+    hart.pc = 12;
+    hart.regs[1] = 300;
+
+    execute(&hart, 0x00a08167); // jalr x2, 10(x1)
+    assert(hart.regs[2] == 16);
+    assert(hart.pc == 310);
+
+    execute(&hart, 0xff608167); // jalr x2, -10(x1)
+    assert(hart.regs[2] == 314);
+    assert(hart.pc == 290);
+}
+
+static void test_branch()
+{
+    struct Hart hart = {0};
+
+    hart.pc = 100;
+    hart.regs[1] = 2;
+    hart.regs[2] = 0xFFFFFFFC;
+
+    execute(&hart, 0x00208c63); // beq x1, x2, 24
+    assert(hart.pc == 104);
+
+    hart.pc = 100;
+    execute(&hart, 0x00209c63); // bne x1, x2, 24
+    assert(hart.pc == 124);
+
+    hart.pc = 100;
+    execute(&hart, 0x0020cc63); // blt x1, x2, 24
+    assert(hart.pc == 124);
+
+    hart.pc = 100;
+    execute(&hart, 0x0020dc63); // bge x1, x2, 24
+    assert(hart.pc == 104);
+
+    hart.pc = 100;
+    execute(&hart, 0x0020ec63); // bltu x1, x2, 24
+    assert(hart.pc == 104);
+
+    hart.pc = 100;
+    execute(&hart, 0x0020fc63); // bgeu x1, x2, 24
+    assert(hart.pc == 124);
+}
+
+static void test_m()
+{
+    struct Hart hart = {0};
+
+    hart.regs[1] = 0xFFFFFFFE;
+    hart.regs[2] = 4;
+
+    execute(&hart, 0x022081b3); // mul x3, x1, x2
+    assert(hart.regs[3] == 0xFFFFFFF8);
+
+    execute(&hart, 0x0220b1b3); // mulhu x3, x1, x2
+    assert(hart.regs[3] == 0x00000003);
+
+    execute(&hart, 0x0220a1b3); // mulhsu x3, x1, x2
+    assert(hart.regs[3] == 0xFFFFFFFF);
+
+    execute(&hart, 0x022091b3); // mulh x3, x1, x2
+    assert(hart.regs[3] == 0xFFFFFFFF);
+
+    hart.regs[1] = 0xFFFFFFFE;
+    hart.regs[2] = 0xFFFFFFFE;
+
+    execute(&hart, 0x022081b3); // mul x3, x1, x2
+    assert(hart.regs[3] == 0x00000004);
+
+    execute(&hart, 0x0220b1b3); // mulhu x3, x1, x2
+    assert(hart.regs[3] == 0xFFFFFFFC);
+
+    execute(&hart, 0x0220a1b3); // mulhsu x3, x1, x2
+    assert(hart.regs[3] == 0xFFFFFFFE);
+
+    execute(&hart, 0x022091b3); // mulh x3, x1, x2
+    assert(hart.regs[3] == 0x00000000);
+
+    hart.regs[1] = (uint32_t)-63;
+    hart.regs[2] = 4;
+    
+    execute(&hart, 0x0220c1b3); // div x3, x1, x2
+    assert(hart.regs[3] == (uint32_t)-15);
+    
+    execute(&hart, 0x0220d1b3); // divu x3, x1, x2
+    assert(hart.regs[3] == 0x3FFFFFF0);
+    
+    execute(&hart, 0x0220e1b3); // rem x3, x1, x2
+    assert(hart.regs[3] == (uint32_t)-3);
+    
+    execute(&hart, 0x0220f1b3); // remu x3, x1, x2
+    assert(hart.regs[3] == 1);
+
+    hart.regs[1] = 30;
+    hart.regs[2] = 0;
+    
+    execute(&hart, 0x0220c1b3); // div x3, x1, x2
+    assert(hart.regs[3] == 0xFFFFFFFF);
+    
+    execute(&hart, 0x0220d1b3); // divu x3, x1, x2
+    assert(hart.regs[3] == 0xFFFFFFFF);
+    
+    execute(&hart, 0x0220e1b3); // rem x3, x1, x2
+    assert(hart.regs[3] == 30);
+    
+    execute(&hart, 0x0220f1b3); // remu x3, x1, x2
+    assert(hart.regs[3] == 30);
+}
+
+int main(int argc, char* argv[])
+{
+    test_addi();
+    test_slti_sltiu();
+    test_andi_ori_xori();
+    test_slli_srli_srai();
+    test_lui_auipc();
+    test_op();
+    test_jal();
+    test_jalr();
+    test_branch();
+    test_m();
+    return EXIT_SUCCESS;
+}

emulator/instruction.h

@@ -0,0 +1,80 @@
+#pragma once
+
+#include <stdint.h>
+
+#include "emulator/bits.h"
+
+struct Instruction
+{
+    uint8_t  opcode;
+    uint8_t  rs1;
+    uint8_t  rs2;
+    uint8_t  rd;
+    uint8_t  funct3;
+    uint8_t  funct7;
+    uint32_t imm;
+};
+typedef struct Instruction Instruction;
+
+static Instruction decode_r_type(uint32_t word)
+{
+    Instruction instruction = {0};
+    instruction.opcode =  word        & 0x7F;
+    instruction.rd     = (word >> 7)  & 0x1F;
+    instruction.funct3 = (word >> 12) & 0x07;
+    instruction.rs1    = (word >> 15) & 0x1F;
+    instruction.rs2    = (word >> 20) & 0x1F;
+    instruction.funct7 =  word >> 25;
+    return instruction;
+};
+
+static Instruction decode_i_type(uint32_t word)
+{
+    Instruction instruction = {0};
+    instruction.opcode =  word        & 0x7F;
+    instruction.rd     = (word >> 7)  & 0x1F;
+    instruction.funct3 = (word >> 12) & 0x07;
+    instruction.rs1    = (word >> 15) & 0x1F;
+    instruction.imm    = sign_extend(word >> 20, 12);
+    return instruction;
+};
+
+static Instruction decode_s_type(uint32_t word)
+{
+    Instruction instruction = {0};
+    instruction.opcode =  word        & 0x7F;
+    instruction.funct3 = (word >> 12) & 0x07;
+    instruction.rs1    = (word >> 15) & 0x1F;
+    instruction.rs2    = (word >> 20) & 0x1F;
+    instruction.imm    = sign_extend(((word >> 7) & 0x1F) | (word >> 25), 12);
+    return instruction;
+};
+
+static Instruction decode_b_type(uint32_t word)
+{
+    Instruction instruction = decode_s_type(word);
+    instruction.imm = ((instruction.imm << 11) & 0x800) | (instruction.imm & 0xfffff7ff);
+    return instruction;
+};
+
+static Instruction decode_u_type(uint32_t word)
+{
+    Instruction instruction = {0};
+    instruction.opcode =  word        & 0x7F;
+    instruction.rd     = (word >> 7)  & 0x1F;
+    instruction.imm    =  word        & 0xFFFFF000;
+    return instruction;
+};
+
+static Instruction decode_j_type(uint32_t word)
+{
+    Instruction instruction = {0};
+    instruction.opcode =  word        & 0x7F;
+    instruction.rd     = (word >> 7)  & 0x1F;
+    instruction.imm    = sign_extend(
+        ((word & 0x80000000) >> 11) |
+        ((word & 0x000FF000) >> 0)  |
+        ((word & 0x00100000) >> 9)  |
+        ((word & 0x7FE00000) >> 20), 21);
+    return instruction;
+}

emulator/lib.c

@@ -0,0 +1,7 @@
+#include "hart.c"
+#include "elf.c"
+#include "csr.c"
+#include "csr_unpriv_counter_timer.c"
+#include "csr_machine_trap_setup.c"
+#include "csr_machine_information.c"
+

emulator/main.c

@@ -0,0 +1,32 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <inttypes.h>
+
+#include "emulator/hart.h"
+#include "emulator/elf.h"
+
+int main(int argc, char* argv[])
+{
+    if (argc < 2)
+    {
+        printf("Usage: %s <input elf>\n", argv[0]);
+        return EXIT_FAILURE;
+    }
+
+    uint32_t mem_size = 16 * 1024 * 1024;
+    char* mem = (char*)malloc(mem_size);
+    uint32_t start_address = 0;
+
+    if (!load_elf(argv[1], mem, mem_size, &start_address))
+    {
+        printf("Error loading ELF into memory\n");
+        return EXIT_FAILURE;
+    }
+
+    struct Hart hart = {0};
+    hart_init(&hart, 0, mem, mem_size);
+
+    execute_from(&hart, start_address);
+
+    return EXIT_SUCCESS;
+}

main.asm

@@ -0,0 +1,22 @@
+.section .text
+.global _main
+
+print:
+    li      t1, 0x80000000
+l0:
+    lb      t0, 0(a0)
+    beqz    t0, l1
+    sb      t0, 0(t1)
+    addi    a0, a0, 1
+    j       l0
+l1:
+    ret
+
+_main:
+    la      a0, my_str
+    call    print
+
+halt: j halt
+
+.section .rodata
+my_str: .string "Hello, world!\n"

main.c

@@ -1,513 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <inttypes.h>
-#include <assert.h>
-#include <stdbool.h>
-
-inline uint32_t sign_extend(uint32_t word, uint32_t size)
-{
-    const uint32_t mask = 1U << (size - 1);
-    return (word ^ mask) - mask;
-}
-
-struct Instruction
-{
-    uint8_t  opcode;
-    uint8_t  rs1;
-    uint8_t  rs2;
-    uint8_t  rd;
-    uint8_t  funct3;
-    uint8_t  funct7;
-    uint32_t imm;
-};
-
-struct Instruction decode_r_type(uint32_t word)
-{
-    struct Instruction instruction = {0};
-    instruction.opcode =  word        & 0x7F;
-    instruction.rd     = (word >> 7)  & 0x1F;
-    instruction.funct3 = (word >> 12) & 0x07;
-    instruction.rs1    = (word >> 15) & 0x1F;
-    instruction.rs2    = (word >> 20) & 0x1F;
-    instruction.funct7 =  word >> 25;
-    return instruction;
-};
-
-struct Instruction decode_i_type(uint32_t word)
-{
-    struct Instruction instruction = {0};
-    instruction.opcode =  word        & 0x7F;
-    instruction.rd     = (word >> 7)  & 0x1F;
-    instruction.funct3 = (word >> 12) & 0x07;
-    instruction.rs1    = (word >> 15) & 0x1F;
-    instruction.imm    = sign_extend(word >> 20, 12);
-    return instruction;
-};
-
-struct Instruction decode_s_type(uint32_t word)
-{
-    struct Instruction instruction = {0};
-    instruction.opcode =  word        & 0x7F;
-    instruction.funct3 = (word >> 12) & 0x07;
-    instruction.rs1    = (word >> 15) & 0x1F;
-    instruction.rs2    = (word >> 20) & 0x1F;
-    instruction.imm    = sign_extend(((word >> 7) & 0x1F) | (word >> 25), 12);
-    return instruction;
-};
-
-struct Instruction decode_b_type(uint32_t word)
-{
-    struct Instruction instruction = decode_s_type(word);
-    instruction.imm = ((instruction.imm << 11) & 0x800) | (instruction.imm & 0xfffff7ff);
-    return instruction;
-};
-
-struct Instruction decode_u_type(uint32_t word)
-{
-    struct Instruction instruction = {0};
-    instruction.opcode =  word        & 0x7F;
-    instruction.rd     = (word >> 7)  & 0x1F;
-    instruction.imm    =  word        & 0xFFFFF000;
-    return instruction;
-};
-
-struct Instruction decode_j_type(uint32_t word)
-{
-    struct Instruction instruction = {0};
-    instruction.opcode =  word        & 0x7F;
-    instruction.rd     = (word >> 7)  & 0x1F;
-    instruction.imm    = sign_extend(
-        ((word & 0x80000000) >> 11) |
-        ((word & 0x000FF000) >> 0)  |
-        ((word & 0x00100000) >> 9)  |
-        ((word & 0x7FE00000) >> 20), 21);
-    return instruction;
-}
-
-struct Hart
-{
-    uint32_t pc;
-    uint32_t regs[32];
-};
-
-void execute_op_imm(struct Hart* hart, uint32_t instruction)
-{
-    const struct Instruction inst = decode_i_type(instruction);
-    if (inst.rd == 0) return;
-    
-    switch (inst.funct3)
-    {
-        case 0: // ADDI
-            hart->regs[inst.rd] = hart->regs[inst.rs1] + inst.imm;
-            break;
-        case 1: // SLLI
-            hart->regs[inst.rd] = hart->regs[inst.rs1] << (inst.imm & 0x1F);
-            break;
-        case 2: // SLTI
-            hart->regs[inst.rd] = (int32_t)hart->regs[inst.rs1] < (int32_t)inst.imm ? 1 : 0;
-            break;
-        case 3: // SLTIU
-            hart->regs[inst.rd] = hart->regs[inst.rs1] < inst.imm ? 1 : 0;
-            break;
-        case 4: // XORI
-            hart->regs[inst.rd] = hart->regs[inst.rs1] ^ inst.imm;
-            break;
-        case 5: // SRLI, SRAI
-        {
-            const uint32_t shamt = inst.imm & 0x1F;
-            uint32_t res = hart->regs[inst.rs1] >> shamt;
-            if ((inst.imm & 0x400) && shamt > 0) { res = sign_extend(res, 32 - shamt); }
-            hart->regs[inst.rd] = res;
-            break;
-        }
-        case 6: // ORI
-            hart->regs[inst.rd] = hart->regs[inst.rs1] | inst.imm;
-            break;
-        case 7: // ANDI
-            hart->regs[inst.rd] = hart->regs[inst.rs1] & inst.imm;
-            break;
-        default:
-            assert(!"Unhandled OP-IMM");
-    }
-}
-
-void execute_op(struct Hart* hart, uint32_t instruction)
-{
-    const struct Instruction inst = decode_r_type(instruction);
-    if (inst.rd == 0) return;
-    
-    switch (inst.funct3)
-    {
-        case 0: // ADD, SUB
-            if (instruction & 0x40000000)
-            {
-                hart->regs[inst.rd] = hart->regs[inst.rs1] - hart->regs[inst.rs2];
-            }
-            else
-            {
-                hart->regs[inst.rd] = hart->regs[inst.rs1] + hart->regs[inst.rs2];
-            }
-            break;
-        case 1: // SLL
-            hart->regs[inst.rd] = hart->regs[inst.rs1] << (hart->regs[inst.rs2] & 0x1F);
-            break;
-        case 2: // SLT
-            hart->regs[inst.rd] = (int32_t)hart->regs[inst.rs1] < (int32_t)hart->regs[inst.rs2] ? 1 : 0;
-            break;
-        case 3: // SLTU
-            hart->regs[inst.rd] = hart->regs[inst.rs1] < hart->regs[inst.rs2] ? 1 : 0;
-            break;
-        case 4: // XOR
-            hart->regs[inst.rd] = hart->regs[inst.rs1] ^ hart->regs[inst.rs2];
-            break;
-        case 5: // SRL, SRA
-        {
-            const uint32_t shamt = hart->regs[inst.rs2] & 0x1F;
-            uint32_t res = hart->regs[inst.rs1] >> shamt;
-            if ((instruction & 0x40000000) && shamt > 0) { res = sign_extend(res, 32 - shamt); }
-            hart->regs[inst.rd] = res;
-            break;
-        }
-        case 6: // OR
-            hart->regs[inst.rd] = hart->regs[inst.rs1] | hart->regs[inst.rs2];
-            break;
-        case 7: // AND
-            hart->regs[inst.rd] = hart->regs[inst.rs1] & hart->regs[inst.rs2];
-            break;
-        default:
-            assert(!"Unhandled OP-IMM");
-    }
-}
-
-void execute_branch(struct Hart* hart, uint32_t instruction)
-{
-    const struct Instruction inst = decode_b_type(instruction);
-    const uint32_t r1 = hart->regs[inst.rs1];
-    const uint32_t r2 = hart->regs[inst.rs2];
-    bool take_branch = false;
-
-    switch (inst.funct3)
-    {
-        case 0: take_branch = (r1 == r2); break;
-        case 1: take_branch = (r1 != r2); break;
-        case 4: take_branch = (r1 < r2); break;
-        case 5: take_branch = (r1 >= r2); break;
-        case 6: take_branch = ((int32_t)r1 < (int32_t)r2); break;
-        case 7: take_branch = ((int32_t)r1 >= (int32_t)r2); break;
-    }
-
-    if (take_branch)
-    {
-        hart->pc += inst.imm;
-    }
-    else
-    {
-        hart->pc += 4;
-    }
-}
-
-void execute(struct Hart* hart, uint32_t instruction)
-{
-    switch (instruction & 0x7f)
-    {
-        case 0x13:
-            execute_op_imm(hart, instruction);
-            hart->pc += 4;
-            break;
-        case 0x17: // AUIPC
-        {
-            struct Instruction inst = decode_u_type(instruction);
-            if (inst.rd != 0)
-            {
-                hart->regs[inst.rd] = inst.imm + hart->pc;
-            }
-            hart->pc += 4;
-            break;
-        }
-        case 0x33:
-            execute_op(hart, instruction);
-            hart->pc += 4;
-            break;
-        case 0x37: // LUI
-        {
-            struct Instruction inst = decode_u_type(instruction);
-            if (inst.rd != 0)
-            {
-                hart->regs[inst.rd] = inst.imm;
-            }
-            hart->pc += 4;
-            break;
-        }
-        case 0x63:
-            execute_branch(hart, instruction);
-            break;
-        case 0x67: // JALR
-        {
-            struct Instruction inst = decode_i_type(instruction);
-            assert(inst.funct3 == 0);
-            if (inst.rd != 0)
-            {
-                hart->regs[inst.rd] = hart->pc + 4;
-            }
-            hart->pc = (hart->regs[inst.rs1] + inst.imm) & 0xFFFFFFFE;
-            break;
-        }
-        case 0x6F: // JAL
-        {
-            struct Instruction inst = decode_j_type(instruction);
-            if (inst.rd != 0)
-            {
-                hart->regs[inst.rd] = hart->pc + 4;
-            }
-            hart->pc += inst.imm;
-            break;
-        }
-        default:
-            assert(!"Unhandled opcode");
-    }
-
-    assert(hart->regs[0] == 0);
-}
-
-void test_addi()
-{
-    struct Hart hart = {0};
-    
-    execute(&hart, 0x00500093); // addi x1, x0, 5
-    assert(hart.regs[1] == 5);
-
-    execute(&hart, 0xffe00093); // addi, x1, x0, -2
-    assert(hart.regs[1] == 0xfffffffe);
-}
-
-void test_slti_sltiu()
-{
-    struct Hart hart = {0};
-    
-    hart.regs[1] = 5;
-
-    execute(&hart, 0x00f0b113); // sltiu x2, x1, 15
-    assert(hart.regs[2] == 1);
-
-    execute(&hart, 0x0050b113); // sltiu x2, x1, 15
-    assert(hart.regs[2] == 0);
-
-    execute(&hart, 0x0010b113); // sltiu x2, x1, 15
-    assert(hart.regs[2] == 0);
-
-    execute(&hart, 0x00f0a113); // slti x2, x1, 15
-    assert(hart.regs[2] == 1);
-
-    execute(&hart, 0x0050a113); // slti x2, x1, 15
-    assert(hart.regs[2] == 0);
-
-    execute(&hart, 0x0010a113); // slti x2, x1, 15
-    assert(hart.regs[2] == 0);
-
-    execute(&hart, 0xffb0a113); // slti x2, x1, -5
-    assert(hart.regs[2] == 0);
-
-    hart.regs[1] = (uint32_t)-20;
-
-    execute(&hart, 0xffb0a113); // slti x2, x1, -5
-    assert(hart.regs[2] == 1);
-}
-
-void test_andi_ori_xori()
-{
-    struct Hart hart = {0};
-    
-    hart.regs[1] = 6;
-
-    execute(&hart, 0x00c0c113); // xori x2, x1, 12
-    assert(hart.regs[2] == 10);
-    
-    execute(&hart, 0x00c0e113); // ori x2, x1, 12
-    assert(hart.regs[2] == 14);
-    
-    execute(&hart, 0x00c0f113); // andi x2, x1, 12
-    assert(hart.regs[2] == 4);
-}
-
-void test_slli_srli_srai()
-{
-    struct Hart hart = {0};
-    
-    hart.regs[1] = 6;
-
-    execute(&hart, 0x00209113); // slli x2, x1, 2
-    assert(hart.regs[2] == 24);
-
-    execute(&hart, 0x0020d113); // srli x2, x1, 2
-    assert(hart.regs[2] == 1);
-
-    execute(&hart, 0x4020d113); // srai x2, x1, 2
-    assert(hart.regs[2] == 1);
-
-    hart.regs[1] = (uint32_t)-6;
-
-    execute(&hart, 0x0020d113); // srli x2, x1, 2
-    assert(hart.regs[2] == 0x3FFFFFFE);
-
-    execute(&hart, 0x4020d113); // srai x2, x1, 2
-    assert(hart.regs[2] == 0xFFFFFFFE);
-}
-
-void test_lui_auipc()
-{
-    struct Hart hart = {0};
-    
-    hart.pc = 0;
-    execute(&hart, 0x0007b0b7); // lui x1, 503808
-    assert(hart.regs[1] == 503808);
-    
-    hart.pc = 0;
-    execute(&hart, 0x0007b097); // auipc x1, 503808
-    assert(hart.regs[1] == 503808);
-    
-    hart.pc = 12;
-    execute(&hart, 0x0007b097); // auipc x1, 503808
-    assert(hart.regs[1] == 503820);
-}
-
-void test_op()
-{
-    struct Hart hart = {0};
-
-    hart.regs[1] = 3;
-    hart.regs[2] = 4;
-    hart.regs[4] = (uint32_t)-1;
-
-    execute(&hart, 0x002081b3); // add, x3, x1, x2
-    assert(hart.regs[3] == 7);
-
-    execute(&hart, 0x402081b3); // sub x3, x1, x2
-    assert(hart.regs[3] == 0xFFFFFFFF);
-
-    execute(&hart, 0x0020a1b3); // slt x3, x1, x2
-    assert(hart.regs[3] == 1);
-
-    execute(&hart, 0x001121b3); // slt x3, x2, 1
-    assert(hart.regs[3] == 0);
-
-    execute(&hart, 0x001131b3); // sltu x3, x2, x1
-    assert(hart.regs[3] == 0);
-
-    execute(&hart, 0x0020b1b3); // sltu x3, x1, x2
-    assert(hart.regs[3] == 1);
-
-    execute(&hart, 0x0040a1b3); // slt x3, x1, x4
-    assert(hart.regs[3] == 0);
-    
-    hart.regs[1] = 6;
-    hart.regs[2] = 12;
-
-    execute(&hart, 0x0020e1b3); // or x3, x1, x2
-    assert(hart.regs[3] == 14);
-
-    execute(&hart, 0x0020c1b3); // xor x3, x1, x2
-    assert(hart.regs[3] == 10);
-
-    execute(&hart, 0x0020f1b3); // and x3, x1, x2
-    assert(hart.regs[3] == 4);
-    
-    hart.regs[1] = 6;
-    hart.regs[2] = 2;
-
-    execute(&hart, 0x002091b3); // sll x3, x1, x2
-    assert(hart.regs[3] == 24);
-
-    execute(&hart, 0x0020d1b3); // srl x3, x1, x2
-    assert(hart.regs[3] == 1);
-
-    execute(&hart, 0x4020d1b3); // sra x3, x1, x2
-    assert(hart.regs[3] == 1);
-    
-    hart.regs[1] = (uint32_t)-6;
-    hart.regs[2] = 2;
-
-    execute(&hart, 0x4020d1b3); // sra x3, x1, x2
-    assert(hart.regs[3] == 0xFFFFFFFE);
-}
-
-void test_jal()
-{
-    struct Hart hart = {0};
-
-    hart.pc = 12;
-
-    execute(&hart, 0x12c000ef); // jal x1, 300
-    assert(hart.regs[1] == 16);
-    assert(hart.pc == 312);
-
-    execute(&hart, 0xed5ff0ef); // jal x1, -300
-    assert(hart.regs[1] == 316);
-    assert(hart.pc == 12);
-}
-
-void test_jalr()
-{
-    struct Hart hart = {0};
-
-    hart.pc = 12;
-    hart.regs[1] = 300;
-
-    execute(&hart, 0x00a08167); // jalr x2, 10(x1)
-    assert(hart.regs[2] == 16);
-    assert(hart.pc == 310);
-
-    execute(&hart, 0xff608167); // jalr x2, -10(x1)
-    assert(hart.regs[2] == 314);
-    assert(hart.pc == 290);
-}
-
-void test_branch()
-{
-    struct Hart hart = {0};
-
-    hart.pc = 100;
-    hart.regs[1] = 2;
-    hart.regs[2] = 0xFFFFFFFC;
-
-    execute(&hart, 0x00208c63); // beq x1, x2, 24
-    assert(hart.pc == 104);
-
-    hart.pc = 100;
-    execute(&hart, 0x00209c63); // bne x1, x2, 24
-    assert(hart.pc == 124);
-
-    hart.pc = 100;
-    execute(&hart, 0x0020cc63); // blt x1, x2, 24
-    assert(hart.pc == 124);
-
-    hart.pc = 100;
-    execute(&hart, 0x0020dc63); // bge x1, x2, 24
-    assert(hart.pc == 104);
-
-    hart.pc = 100;
-    execute(&hart, 0x0020ec63); // bltu x1, x2, 24
-    assert(hart.pc == 104);
-
-    hart.pc = 100;
-    execute(&hart, 0x0020fc63); // bgeu x1, x2, 24
-    assert(hart.pc == 124);
-}
-
-void test()
-{
-    test_addi();
-    test_slti_sltiu();
-    test_andi_ori_xori();
-    test_slli_srli_srai();
-    test_lui_auipc();
-    test_op();
-    test_jal();
-    test_jalr();
-    test_branch();
-}
-
-int main(int argc, char* argv[])
-{
-    test();
-    return EXIT_SUCCESS;
-}

os/.gitignore

@@ -0,0 +1 @@
+build/

os/boot.S

@@ -0,0 +1,31 @@
+.option norvc
+
+.section .init
+
+.equ UART_BASE, 0x10000000
+
+.global kstart
+kstart:
+    la        a0, _str
+    call      _println
+
+_halt:
+    wfi
+    j         _halt
+
+_println:
+    li        t0, UART_BASE
+_println_loop:
+    lb        t1, 0(a0)
+    beqz      t1, _end_println_loop
+    sb        t1, 0(t0)
+    addi      a0, a0, 1
+    j         _println_loop
+_end_println_loop:
+    li        t1, '\n'
+    sb        t1, 0(t0)
+    ret
+
+.section .rodata
+
+_str: .string "Hello, world!"

os/build.bat

@@ -0,0 +1,7 @@
+@echo off
+
+IF NOT EXIST build mkdir build
+
+clang --target=riscv32 -march=rv32im -nostdlib boot.S -c -o build\boot.o
+
+ld.lld -T linker.ld build\boot.o -o build\kernel.elf

os/linker.ld

@@ -0,0 +1,23 @@
+ENTRY(kstart);
+
+MEMORY {
+  ram (wxa) : ORIGIN = 0x80000000, LENGTH = 128M
+}
+
+PHDRS {
+  text   PT_LOAD;
+  rodata PT_LOAD;
+}
+
+SECTIONS {
+  .text : ALIGN(4K) {
+    *(.init);
+    *(.text);
+  } >ram AT>ram :text
+
+  .rodata : ALIGN(4K) {
+    *(.rodata);
+  } >ram AT>ram :rodata
+}
+
+ # @Todo .bss (clear), .data, etc

os/notes.txt

@@ -0,0 +1,32 @@
+qemu-system-riscv32 -machine virt -cpu rv32 -smp 1 -m 128M -nographic -serial mon:stdio -bios none -kernel kernel.elf
+
+qemu-system-riscv32 -machine virt -cpu rv32 -smp 1 -m 128M -bios none -kernel kernel.elf
+
+cmd /c exit
+
+clang --target=riscv32 -march=rv32im -nostdlib boot.S -c -o boot.o
+
+ld.lld -T linker.ld boot.o -o kernel.elf
+
+static const MemMapEntry virt_memmap[] = {
+    [VIRT_DEBUG] =        {        0x0,         0x100 },
+    [VIRT_MROM] =         {     0x1000,        0xf000 },
+    [VIRT_TEST] =         {   0x100000,        0x1000 },
+    [VIRT_RTC] =          {   0x101000,        0x1000 },
+    [VIRT_CLINT] =        {  0x2000000,       0x10000 },
+    [VIRT_ACLINT_SSWI] =  {  0x2F00000,        0x4000 },
+    [VIRT_PCIE_PIO] =     {  0x3000000,       0x10000 },
+    [VIRT_PLATFORM_BUS] = {  0x4000000,     0x2000000 },
+    [VIRT_PLIC] =         {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
+    [VIRT_APLIC_M] =      {  0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
+    [VIRT_APLIC_S] =      {  0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
+    [VIRT_UART0] =        { 0x10000000,         0x100 },
+    [VIRT_VIRTIO] =       { 0x10001000,        0x1000 },
+    [VIRT_FW_CFG] =       { 0x10100000,          0x18 },
+    [VIRT_FLASH] =        { 0x20000000,     0x4000000 },
+    [VIRT_IMSIC_M] =      { 0x24000000, VIRT_IMSIC_MAX_SIZE },
+    [VIRT_IMSIC_S] =      { 0x28000000, VIRT_IMSIC_MAX_SIZE },
+    [VIRT_PCIE_ECAM] =    { 0x30000000,    0x10000000 },
+    [VIRT_PCIE_MMIO] =    { 0x40000000,    0x40000000 },
+    [VIRT_DRAM] =         { 0x80000000,           0x0 },
+};

os/run.bat

@@ -0,0 +1,5 @@
+@echo off
+
+qemu-system-riscv32 -machine virt -cpu rv32 -smp 1 -m 128M -nographic -serial mon:stdio -bios none -kernel build\kernel.elf
+
+cmd /c exit